For its high-density and relatively short cycle time, the DRAM (Dynamic Random Access Memory) is utilized extensively as a main memory in computer systems, even though DRAM requires refresh cycle to sustain stored data within a predetermined refresh time. As such, the DRAM constitutes a key component that holds sway on the performance of the computer system. Efforts of research and development have been under way primarily to boost the speed of the memory.
In the conventional DRAM, hierarchical bit line architecture is applied in order to achieve high-speed operation, as published, “Hierarchical bitline DRAM architecture system” as U.S. Pat. No. 6,456,521, and “A hierarchical bit-line architecture with flexible redundancy and block compare test for 256 Mb DRAM” in VLSI Circuits, Digest of Technical Papers, May 1993. pp 93-94. More specifically, FIG. 1 illustrates a circuit diagram of the conventional DRAM. The memory cells 101 and 102 are connected to a local bit line 131, and the memory cells 103 and 104 are connected to another local bit line 133, where the plate of capacitor is connected half VDD typically. Local bit lines 131 and 133 are connected to a global bit line (BLT) 111 and another global bit line (BLB) 112 through transfer transistors 121 and 123, respectively. And more local bit lines 132 and 134 are connected to the global bit lines 111 and 112, respectively. When reading, one of memory cells is selected, and the selected cell charges or discharges the local bit line while the local bit lines and the global lines are released from pre-charge node 117, such that equalizer transistor 113, pre-charge transistors 114 and 115 are turned off by control signal 116. Thus, one of global bit lines is also charged or discharged by the selected memory cell. After then sense amplifier 141 is activated to generate read output 142. However, the selected global bit line is slowly changed because the selected memory cell should drive local bit line and global bit line through transfer transistor. Moreover, the storage capacitor in the memory cell should be relatively big in order to absorb the charges from the global bit line, which is one of major obstacles to reduce the DRAM cell. As a result, access time is also slow because of heavy global bit line, which increases propagation delay and sensing time for the sense amplifier.
In this respect, there is still a need for improving the dynamic random access memory, in order to achieve fast access and reduce cell area. In the present invention, the bit lines are multi-divided bit line to reduce the parasitic capacitance of the local bit line, and a segment read circuit is added for reading the local bit line more effectively, because the segment read circuit is composed of a few transistors to insert in the memory array. And, a time-domain sensing scheme is introduced in order to differentiate low voltage data and high voltage data in the time-domain, which does not require the conventional sense amp.
And one of major advantages of the present invention is that there is no need for forming extreme feature size transistors because the memory cells can be stacked over the control circuit. In stead of scaling the transistors to extreme geometry, topping memory cells including thin film transistor is more practical, which also achieves fast access with centralized control and short routing length in vertical direction. As a result, there is no scaling limit to fabricate the memory chip by topping multiple memory cells. More detailed explanation will be followed as below.